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maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. ds3 3 z 1 1 de m o k it ge ne ra l de sc ript ion the ds33z11 demo kit is an easy-to-use evaluation board for the ds33z11 ethernet transport-over-serial link device. the DS33Z11DK contains an integrated ethernet phy and serial link. the serial link is complete with transceiver, transformers, and network connections. maxims chipview software is provided with the demo kit, giving point-and-click access to configuration and status re gisters from a windows ? - based _ pc. on-board leds indicate receive loss-of- signal, queue overflow, ethernet link, tx/rx, and interrupt status. windows is a registered trademark of microsoft corp. de m o k it cont e nt s DS33Z11DK main board 5.0v wall adapter bnc adapter (2-pin coax) cd-rom chipview software and manual DS33Z11DK data sheet configuration files orde ring i nform a t ion part type DS33Z11DK ds33z11 demo kit fe a t ure s ? demonstrates key functions of ds33z11 ethernet transport chipset ? on-board ds2155 t1e1 sct, ds3170 t3e3 sct, transformers, bnc adapter, and rj48 network connectors and termination ? provides support for hardware and software modes ? device driver provides automatic configuration for t1, e1, t3, and e3 modes ? on-board mmc2107 processor and chipview software provide point-and-click access to the ds33z11, ds2155, and ds3170 register sets ? all ds33z11 interface pins are easily accessible for external data source/sink ? leds for loss-of-signal, queue overflow, ethernet link, tx/rx, and interrupt status ? easy-to-read silkscreen labels identify the signals associated with all connectors, jumpers, and leds ? integrated power-supply interfaces with 5.0v wall adapter rev: 080508 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 2 of 34 table of contents 1. system floorplan.................................................................................................................... 3 2. pcb errata .................................................................................................................................. 3 3. basic operation ................................................................................................................ ........ 3 3.1 p owering u p the d emo k it .......................................................................................................... 3 3.2 i nstalling and r unning the s oftware ....................................................................................... 4 3.3 f ile l ocations .............................................................................................................................. 4 4. basic ds33z11 initialization (used for all quick setups)......................................... 5 4.1 q uick s etup #1 (d evice d river + t1 or e1) ............................................................................... 5 4.2 q uick s etup #2 (d evice d river + t3 or e3) ............................................................................... 5 4.3 q uick s etup #3 (ds2155 t1e1)................................................................................................... 6 4.4 q uick s etup #4 (ds3170 t3e3)................................................................................................... 6 5. monitor and capture ethernet traffic ......................................................................... 6 6. leds configuration switches and jumpers.................................................................. 7 7. address map .................................................................................................................... ......... 10 8. ds33z11 information .............................................................................................................. 10 8.1 DS33Z11DK i nformation ........................................................................................................... 10 8.2 t echnical s upport .................................................................................................................... 10 9. component list........................................................................................................................ 11 10. schematics ..................................................................................................................... ........... 14 11. revision history............................................................................................................... ....... 15 list of figures figure 1. serial jump er confi guration .......................................................................................... ............................... 7 list of tables table 1. main board pcb configuration .......................................................................................... ........................... 7 table 2. overview of da ughter card address map................................................................................. .................. 10 table 3. com ponent list........................................................................................................ .................................... 11 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 3 of 34 1. system floorplan 2. pcb errata ? the following errata apply to DS33Z11DK02a0: o ds33z11 rser and tser wires were crossed. the schematic has been corrected, and pcbs have been reworked to match the schematic. o header j04 pins 1, 3, 5, 7, 9 were not conne cted to vcc. the schematic has been corrected, and pcbs have been reworked to match the schematic. 3. basic operation note: in the following sections, software-related items are identified by bolding. text in bold refers to items directly from the ev kit software. text in bold and underlined refers to items from the windows operating system. 3.1 powering up the demo kit ? connect pcb 5.0v wall adapter to the power jack. led ds11 should light. ? connect rs232 serial cable, or usb cable between the host pc and demo kit. ? connect the ethernet port to an ordinary pc, or network test equipment. either a patch or crossover cable may be used. the link led should turn on after connecting the cable. ? set jumpers for software mode as described in table 1 (short description follows). ? top bank all gnd (dcedte .. scanen), with exception for modec0 which is at vcc ? a2, a1, a0 jumpered to pins 2+3 ? right bank all to vcc (afcs, fullds, h1os) ? upon power-up, the processor fpga status leds (ds07 green) will be lit. interrupt leds (ds09 red) will not be lit. ds33z11 queue overflow leds (ds10 red) will not be lit. phy link led (ds02/ds01 green) should be lit if the ethernet is connected. ds33z11 sdram ethernet phy magnetic leds and jumpers serial selection jumpers transformer and network connections (ds2155) transformer and network connections (ds3170) fpga a ddress databus testpoints once debug sysclk reflck osc and selection hardware mode switches for ds33z11 hardware mode switches for ds33z11 system power (5.0 v) microprocessor serial port (57600-8n1) usb ds3170 ds2155 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 4 of 34 3.2 installing and running the software chipview is a general-purpose program that supports a number of maxim demo kits. to install the chipview software, run setup.exe from the disk included in the DS33Z11DK box or from the zip file downloadable on our website at www.maxim-ic.com/DS33Z11DK . after installation, run the chipview program with t he DS33Z11DK board powered up and connected to the pc. if the default installation options were used, one easy way to run chipview is to click the start button on the windows toolbar and select programs chipview chipview . in the opening screen, click the register view button. select the correct serial (or usb) port in the port selection dialog box, then click ok . next, the definition file assignment window appears. this window has subwindows to select definition files for up to four separate boards on other maxim evaluation platfo rms. in the active subwindo w, select the ds33z11.def definition file from the list shown, or browse to find it in another directory. press the continue button. after selecting the definition file, the main part of the ch ipview window displays the ds33z11 register map. other definition files may be loaded, and navigated to using the m enu marked def file selection. to select a register, click on it in the register map. when a register is select ed, the full name of the register and its bit map are displayed at the bottom of the chipview window. bits that are logic 0 are displayed in white, while bits that are logic 1 are displayed in green. the chipview software supports the following actions: ? toggle a bit. select the register in the register m ap and then click the bit in the bit map. ? write a register. select the register, click the write button, and enter the value to be written. ? write all registers. click the write all button and enter the value to be written. ? read a register. select the register in the register map and click the read button. ? read all registers. click the read all button. ? navigate to def file. select from the def file selection menu 3.3 file locations this demo kit relies upon several supporting files, which are provided on the cd and are available as a zip file from the maxim website at www.maxim-ic.com/DS33Z11DK . all locations are given relative to the top directory of the cd/zip file. ? ds33z11 register definition f iles and configuration files: o .\cfg_demo_gui\ds33z11_cfg_demo_gui\ds33z11.def o .\ds33z11_cfg_demo_gui\su_li_port1.def o .\ds33z11_cfg_demo_gui\basic_config.mfg ? ds2155 register definition file s and configuration files: o .\ds33z11_cfg_demo_gui\te1_ds2155\ds2155.def o .\ds33z11_cfg_demo_gui\te1_ds2155\e1_gapclk_crc4_hdb3_nocas.ini ? ds3170 register definition file s and configuration files: o .\ds33z11_cfg_demo_gui\te3_ds3170\ _ds3170_global.def o .\ds33z11_cfg_demo_gui\te3_ds3 170\ ds3170_port_liu.def o .. 6 other low level def files . o .\ds33z11_cfg_demo_gui\te3_ds3170\ 70_t3_sct_needscoaxlb.mfg downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 5 of 34 4. basic ds33z11 initialization (used for all quick setups) this section covers four basic methods for configuring the ds33z11. any one of these initializations can be used with the following quick setup examples: 1. device driver based. if pins j04.1+j04.2 are jumpered, the on-board device driver provides a basic configuration for the ds33z11. this enables traffic to pass from the ethernet port to the serial port. consult the device driver documentation for further details. sections 4.1 and 4.2 describe specific device driver based configurations. to load the gui interface for t he device drivers go to the chipview register mode tools menu and select t ools p lugins ds33xw device driver demo. 2. register-based configuration. launch chipview.exe and select register view. sections 4.3 and 4.4 describe specific configurations. 3. hardware mode. set switches as described in the section for powering up the demo kit, then change the following: hwmode 3.3v, a0 3.3vv, a1 3.3v, a2 0v. this sets the part fo r lsb first, scrambling off, hdlc encapsulated. at this point traffic will pass from the ethernet port to the serial port. in this mode broadcast frames are not passed (i.e., ping). 4. eeprom mode is available with the dk , but is beyond the scope of this manual. 4.1 quick setup #1 (device driver + t1 or e1) ? install jumpers to place the serial interface in t1e1 mode as shown in figure 1. ? complete the hardware configuration and one of the basic ds33z11 configurations as described in the previous section. (ensure jumpers for j04.1+j 01.2 are installed to enable the device driver). ? remove jumper between j04.9 and j04.10: ? install jumper between j04.7 and j04.8 for e1 mode. remove jumper between j04.7 and j04.8 for t1 mode. ? place a loopback connector at the ds2155 network side; rlos led ds13 should go out. ? at this point any packets sent to the ds33z11 are echoed back. incoming packets (i.e., ping) should cause the act led to blink. ? to interact with the device driver select from the drop down menu: ? tools plugins load plugins. when asked if dlls hav e already registered select yes ? select tools plugins ds33z44/11/41 device driver demo ? a new form called zchip configuration pops up. ? preload basic configuration for the gui by selecting file load settings (in the zchip configuration form). select the file named basic_config.eset 4.2 quick setup #2 (device driver + t3 or e3) ? install jumpers to place the serial interface in t3e3 mode as shown in figure 1. ? complete the hardware configuration and one of the basic ds33z11 configurations as described in the previous section. (ensure jumpers for j04.1+j 01.2 are installed to enable the device driver). ? install jumper between j04.9 and j04.10: ? install jumper between j04.7 and j04.8 for e3 mode. remove jumper between j04.7 and j04.8 for t3 mode. ? place jumpers to loopback the ds3170 netwo rk side; rlos led ds12 should go out. ? at this point any packets sent to the ds33z11 are echoed back. incoming packets (i.e., ping) should cause the act led to blink. ? to interact with the device driver select from the drop down menu: ? tools plugins load plugins. when asked if dlls hav e already registered select yes ? select tools plugins ds33z44/11/41 device driver demo ? a new form called zchip configuration pops up. ? preload basic configuration for the gui by selecting file load settings (in the zchip configuration form). select the file named basic_config.eset downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 6 of 34 4.3 quick setup #3 (ds2155 t1e1) ? install jumpers to place the serial interface in t1e1 mode as shown in figure 1. ? complete the hardware configuration and one of the basi c ds33z11 configurations as previously described. ? launch chipview.exe (or use existing session if its already open) and select register view. when prompted for a definition file, pick the file named ds33z11.def . after the definition file loads, go to the file menu and select f ile m emory config file l oad .mfg file. when prompted, select the file named basic_config.mfg . ? load the definition file for the ds2155 by going to the file menu and selecting f ile d efinition config file and select the definition file named ds2155.def . after the definition file loads, go to the file menu and select f ile r eg ini file l oad ini file. when prompted, pick the file named e1_gapclk_crc4_hdb3_nocas.ini . ? place a loopback connector at the ds2155 network side; rlos led ds35 should go out. ? at this point any packets sent to the ds33z11 are echoed back. incoming packets (i.e., ping) should cause the act led to blink. 4.4 quick setup #4 (ds3170 t3e3) ? install jumpers to place the serial interface in t3e3 mode as shown in figure 1. ? complete the hardware configuration and one of the basi c ds33z11 configurations as previously described. ? launch chipview.exe (or use existing session if its already open) and select register view. when prompted for a definition file, pick the file named ds33z11.def . after the definition file loads, go to the file menu and select f ile m emory config file l oad .mfg file. when prompted, select the file named basic_config.mfg . ? load the definition file for the ds3170 by going to the file menu and selecting f ile d efinition config file and select the definition file named ds3170_global.def . after the definition file loads, go to the file menu and select f ile m emory config file l oad .mfg file. when prompted, select the file named 70_t3_sct_needscoaxlb.mfg . ? place a loopback connector at the ds3170 network side. ? at this point any packets sent to the ds33z11 are echoed back. incoming packets (i.e., ping) should cause the act led to blink. 5. monitor and capture ethernet traffic ? although ping is mentioned, it is *not* recommended. the ping command goes through the computers tcpip stack, and sometimes will not be sent out the pcs netw ork connector (i.e., if the pcs arp cache is out of date). additionally ping requires two pcs, as a pc with only one adapter can not ping itself (a local ping gets sent to local host instead of out the connector). with t hat said, ping is still a valuable test once the prototyping stage is complete. ? generation and capture of arbitrary (raw) packets can be easily accomplished using commview. a time-limited demo is available at the website www.tamos.com/products/commview. ? wireshark is an excellent (and free) packet capture utility. download is available at ww w.wireshark.org. ? adding additional ethernet ports to a pc is rather simple when a usb-to-ethernet adapter is used. this allows for end-to-end testing using a single pc. when using two adapters the pc will have a different ip address for each adapter. test equipm ent will allow selection of ei ther adapter. operating system based network traffic will be sent out the default adapter, usually this is the adap ter that has recently had connection to a live network. downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 7 of 34 figure 1. serial jumper configuration 6. leds configurati on switches and jumpers the DS33Z11DK has several configuration swit ches, banana plugs, osc illators, and jumpers. table 1 provides a description of these components, given in order of appearance on the pcb. component listing is given from left to right, top to bottom, when the board is held with the ethernet port at the top. table 1. main board pcb configuration basic setting silkscreen reference function sw mode hw mode description j01 system power installed installed power jack +5.0v to center post j02 ethernet connection installed installed ethernet connection with mdix, connect with ether a patch or crossover cable jp01 jp02 jp03 dp83848 an0 an1 an_en not installed * not installed* configuration pins for dp83848 phy. these pins have internal pullups. leaving un-jumpered or setting to vcc enables auto-negotiation and advertise as 100/10 full/half duplex capable. ds02+ds01 ds04+ds03 ds06+ds05 link (on for link) speed (on for 100) activity (blink for act) on on blink on on blink status leds for dp83848 phy. each status function has 2 leds to accommodate the pin configuration methods used by the phy jp12 dp83848 mdix vcc vcc set to vcc to enable mdix (automatic crossing of rx/tx pair) jp14 dp83848 rmii gnd gnd set to gnd to enable mii mode, vcc to enable rmii mode. note that the ds33z11 rmii pin needs to be jumpered to match this pin. jp11 ds33z11 mode pin; dte/dce selection low low low for dte jp10 ds33z11 mode pin rmii/mii selection low low high for rmii, low for mii hardware loopback (unused, requires external wire) t1e1 mode (ds2155) t3e3 mode (ds3170) jp20 rser jp21 tser jp22 tclki jp23 rclki external oscillator jp20 rser jp21 tser jp22 tclki jp20 rser jp21 tser jp22 tclki jp23 rclki jp23 rclki downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 8 of 34 basic setting silkscreen reference function sw mode hw mode description jp09 ds33z11 mode pin ckpha selection low low spi eeprom hardware mode configuration switch jp08 ds33z11 mode pin modec0 selection high low software mode selected jp07 ds33z11 mode pin modec1selection low low software mode selected jp06 ds33z11 mode pin hwmode selection low low hardware/software mode (software mode selected) jp04 ds33z11 mode pin scanmo selection low low set low for normal operation jp05 ds33z11 mode pin scanen selection low low set low for normal operation j03 usb user decision user decision system usb connector. used with chipview host pc software (if rs232 is not used) j10 rs232 serial user decision user decision system rs232 connector. used with chipview host pc so ftware (if usb is not used). the rs232 connector may also be used with any terminal emulator, settings are 57.6k, 8n1, no flow control. ds07 status led on on displays kit status. this led should remain lit ds08 status led - - mi scellaneous led. j04.1 + j04.2 enable device driver user decision when installed the device driver will configure the ds33z11 and the transceiver during power-up. j04.3 + j04.4 enable callbacks user decision when installed the driver will respond to interrupts. j04.3 + j04.4 looptime / sourcetime user decision when installed the driver will configure the serial link for looptime (tclk driven by rclk). when not installed tclk is driven by scaled mclk. driver must be enabled to make use of this setting. j04.7 + j04.8 j04.9 + j04.10 t1e1, t3e3 selection not installed when installed the driver will select a transceiver and mode of operation as shown below. 00 = ds2155 in t1 mode 01 = ds3170 in t3 mode 10 = ds2155 in e1 mode 11 = ds3170 in e3 mode driver must be enabled to make use of these settings. jp18 jp17 jp16 addr2 addr1 addr0 installed pins 2+3 see ds33z11 datasheet address pin/eeprom config switch. install on pins 2+3 to connect ds33z11 address pins a2,a1,a0 to the processor. leave disconnected to allow pullup to pull high. connect pins 1+2 to pull low. j07 jtag jtag testpoints for ds33z11 j06, j05 ethernet testpoints testpoints for ethernet interface yb02 (bottom side) unused refclk osc unused oscillator. could be used to drive ds33z11 refclk and phy mclk. instead this oscillator is not used, and the clocks are provided by ds33z11 refclko. downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 9 of 34 basic setting silkscreen reference function sw mode hw mode description jp24 refclk / phy clock selection ds33z11 refclk output. jumper pins 1+2 to drive with yb02. jumper pins 2+3 to drive with ds33z11 refclk output. yb03 (bottom side) system clock system clock for ds33z11. must be set for 100mhz if refclko is used to drive refclki and phyclk. y01 (not populated) spi_cs, spi_ck, spi_miso, spi_mosi spi signals (for eeprom memory) jp13 ds33z11 mode pin afcs selection hw mode only high set high to enable auto flow control. jp15 ds33z11 mode pin fullds selection hw mode only high set high to enable full duplex. jp19 ds33z11 mode pin h10s selection hw mode only high set high to confg for 100mb u04 processor testpoints -- -- testpoint grid surrounding processor, all processor pins are brought out. j09 j08 address databus address databus for ds33z11, ds2155, ds3170. unused chipselect cs_x4 are provided to allow the dk to control additional, external devices. j08.12+j08.14 fpga tristate jumper setting the tristate jumper will tristate the fpga. this provides the user with a method for controlling the dk with an external processor. tp02 refclkin testpoint ds33z11 refclk input. also see jp24. sw01 system reset drives ub11 reset controller ds11 led power ok led j13 debug connector for once software debug j12 jtag jtag connector for lattice fpga tp05 tp06 tden rden ds33z11 tden rden testpoints. unused. jp20 jp21 jp22 jp23 tser rser tclki rclki jumpered, see figure 1 jumpered, see figure 1 jumper selection for serial interface. possible modes are: t1e1, t3e3, loopback (or wired to external system). note that loopback requires an external oscillator to be wired in. jp25 testpoints t3e3_osc testpoints for t3e3 oscillator. can be used as tclk/rclk when in hardware loopback yb04 osc oscillato r for ds2155 mclk j14 j16 2-pin bnc jumper jumper for connection to t1e1 bnc j15 rj45 t1e1 rj45 connector ds13 led ds2155 rlos led ds12 led ds3170 gpio led j18 j17 tx rx jumper for connection to t3e3 bnc downloaded from: http:///
_______________________________________________________________________________ ds3 3 z 1 1 dk rev: 080508 10 of 34 7 . addre ss m a p motorola resource card address space begins at 0x81 000000. all offsets given below are relative to 0x81000000. table 2. overview of daughter card address map offset device description 0x0000 to 0x0087 fpga processor board identification 0x1000 to 0x1fff ds33z11 ds33z11. uses cs_x1. 0x2000 to 0x2fff ds2155 t1e1 transceiver. uses cs_x2 0x3000 to 0x3fff ds3170 t3e3 transceiver. uses cs_x3. 0x4000 to 0x4fff unused unused chipselect for controlling external device. uses cs_x4. registers in the ds33z11, ds2155, and ds3170 can be easily modified using the chipview host-based user- interface software with the definit ion files previously mentioned. 8 . ds3 3 z 1 1 i nform a t ion for more information about the ds33z11, consult th e ds33z11 data sheet available on our website at www.maxim-ic.com/ds33z11 . 8 .1 ds3 3 z 1 1 dk i nform a t ion for more information about the DS33Z11DK, including so ftware downloads, consult the DS33Z11DK data sheet available on the our website at www.maxim-ic.com/DS33Z11DK . 8 .2 t e c hnic a l support for additional technical support, go to www.maxim-ic.com/support . downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 11 of 34 9. component list table 3 shows the component list for the DS33Z11DK. table 3. component list designation qty description supplier part c01, c02, c03, c04, c05, c06, c07, cb22, cb28, cb73 , c14, c16, c20, cb44, cb56 15 1206 ce ram 10uf 10v 20% panasonic ecj-3yb1a106m see next row (begins with c08) 34 l_0603 ceram .01uf 50v 10% x7r avx 06035c103kat c08, c17, c22, c27, c29, c36, c37, c40, c41, c42, cb05, cb11, cb17, cb 18, cb19, cb27, cb35, cb40, cb46, cb47, cb54, cb57, cb59, cb65, cb69, cb78, cb80, cb82, cb84, cb90, cb91, cb94, cb97, cb99 31 l_0603 ceram .1uf 16v 20% x7r avx 0603yc104mat c09, c18, c24, c38, c39, c45, cb 08, cb13, cb29, cb32, cb33, cb34, cb37, cb39, cb45, cb50, cb55, cb58, cb60, cb63, cb67, cb70, cb71, cb74, cb76, cb86, cb87, cb88, cb93, cb95, cb96 c10, c11 2 l_0603 ceram 22pf 25v 5% npo avx 06033a220jat c12, c13 , c44 3 l_1206 ceram 1uf 16v 10% panasonic ecj-3yb1c105k see next row (begins with c15) 51 0603 ceram 4.7uf 6.3v multilayer unk ecj-1vb0j475m c15, c21, c23, c25, c26, c28, c30, c31, c32, c33, c34, c35, c43, c46, c47, cb09, cb10, cb15, cb20, cb21, cb24, cb25, cb26, cb30, cb31, cb36, cb38, cb41, cb42, cb43, cb48, cb49, cb51, cb52, cb53, cb61, cb62, cb64, cb66, cb68, cb72, cb75, cb77, cb79, cb81, cb83, cb85, cb89, cb92, cb98, cb100 c19, cb04, cb06, cb07, cb14, cb16, cb23 7 0603 ceram 0.1uf 16v 10% phycomp 06032r104k7b20d cb01, cb02, cb03, cb12 4 l_d case tant 68uf 16v 20% panasonic ecs-t1cd686r db01 1 schottky diode, 1 amp 40 volt international rectifier 10bq040 ds01, ds02, ds07 , ds11 4 l_led, green, smd panasonic ln1351c ds03, ds04 2 led, amber, smd panasonic ln1451c ds05, ds06, ds13 , ds08, ds09, ds10, ds12 7 led, red, smd panasonic ln1251c gnd_tp01, gnd_tp02, gnd_tp03, gnd_tp04, gnd_tp05, gnd_tpb01 6 standard ground clip keystone 4954 h01, h02, h03, h04, h05, h06 6 kit, 4-40 hardware, .50 nylon standoff and nylon hex-nut na 4-40kit4 j01 1 conn 2.1mm/5.5mm pwrjack rt angle pcb, closed frame, high current 24vdc@5a also requires 5v acdc adapter input 100-240vac 50- 60hz 0.6a output dc 5v 2.6a. pn dms050260-p5p-sz. model 3z- 161wp05 cui, inc pj-002ah j02 1 connector, fastjack single, 8 pin for national phy halo electronics hfj11-2450e j03 1 type b single rt angle, black mol na j04 1 terminal strip, 10 pin, dual row, vert na na j05, j06 2 l_terminal strip, 10 pin, dual row, vert do not populate dnp dnp downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 12 of 34 designation qty description supplier part j07, j12 2 l_terminal strip, 10 pin, dual row, vert samtec tsw-105-07-t-d j08, j09 2 non populated header, 14 pin, dual row, vert samtec nopop-hdr-tsw-107- 14-t-d j10 1 l_conn, db9 ra, long case amp 747459-1 j11 1 100 mil 2 pos jumper na na j13 1 100 mil 2*7 pos jumper na na j14, j16, j17, j18 4 l_2 pin header, .100 centers, vertical samtec tsw-102-07-t-s j15 1 l_rj48 8 pin single port connector molex 15-43-8588 see next row (begins with jp01) 23 100 mil 3 pos jumper na na jp01, jp02, jp03, jp04, jp05, jp06, jp 07, jp08, jp09, jp10, jp11, jp12, jp13, jp14, jp15, jp16, jp17, jp18, jp19, jp20, jp21, jp22, jp23, jp24 r01, r1, r2, r3, r4, r5, r6, r7, r8, r9, r05, r15, r16, r17, r18, rb06, rb16 17 res 0603 2.2k ohm 1/16w 5% panasonic erj-3geyj222v r02, rb25, rb26, rb29, rb43 , rb24 6 l_res 0603 330 ohm 1/16w 5% panasonic erj-3geyj331v see next row (begins with r03) 19 res 0603 30 ohm 1/16w panasonic erj-3geyj300v r03, r04, r06, r07, rb32, rb36, rb37, rb38, rb39, rb40 , r13, rb19, rb 21, rb23, rb41, rb42, rb48, rb53, rb54 r09 1 res 0603 1.0m ohm 1/16w 5% panasonic erj-3geyj105v r10, r11, r12, r14 4 l_res 0805 0.0 ohm 1/10w 5% panasonic erj-6gey0r00v rb01, rb02, rb03, rb04, rb05, rb22, rb34 7 res 0603 0.0 ohm 1/16w 5% panasonic erj-3gey0r00v rb07 1 res 0603 4.87k ohm 1/16w 1% panasonic erj-3ekf4871v rb18, rb20 , rb28, rb30, rb35, rb51 6 res 0603 10k ohm 1/16w 5% panasonic erj-3geyj103v rb33 1 res 0805 10k ohm 1/10w 1% panasonic erj-6enf1002v rb44, rb46 2 res 0805 61.9 ohm 1/10w 1% panasonic erj-6enf61r9v rb49, rb50 2 res 0603 332 ohm 1/16w 1% panasonic erj-3ekf3320v rb52 1 res 0805 330 ohm 1/10w 5% panasonic erj-6geyj331v rp01 1 4 pack resistor 50 ohm 2 pct koa cn1j4ttd500g or cn1j4ttd49r9f rp02, rpb01, rpb03, rpb04, rpb05 5 4 pack resistor 2.2k ohm 5% quad 0402 panasoni c exb-n8v222jx rp03, rp04, rp05, rpb06 4 4 pack resistor 30 ohm 5% quad 0402 panasonic exb-n8v300jx see next row (begins with rp06) 17 4 pack resistor 10k ohm 5% quad 0402 panasonic exb-n8v103jx rp06, rp07, rp08, rpb08, rpb09, rpb10, rpb11, rpb12, rpb13, rpb14, rpb16, rpb17, rpb18, rpb19, rpb20, rpb21, rpb22 rpb02, rpb07, rpb15 3 4 pack resistor 330 ohm 5% quad 0402 panasonic exb-n8v331jx sw01 1 l_switch mom 4pin sing le pole panasonic evqpae04m t01 1 xfmr 16p smt pulse tx1099 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 13 of 34 designation qty description supplier part t02 1 xfmr, octal t3/e3, 1 to 2, smt 32 pin pulse t3049 tp01, tp02, tp03, tp04, tp05, tp06, tpb01, tpb02, tpb03, tpb04 10 testpoint, 1 plated hole, do not stuff na na u01 1 ic, dp83848c phyter 10/100 ethernet transceiver, 48 pin tqfp national semiconduct or dp83848c u02 1 usb uart (usb - 8 bit fifo), 32 pin lqfp ftd ft245bm u03 1 elite 10/100 ethernet transport over serial link 14x14 csbga 169 pin maxim ds33z11 u04 1 mmc2107 processor motorola mmc2107 u05 1 ic, fpga, 1.2v, 20x20 tqfp, 144 pin lat lfec3e-3t144c u06, ub13 2 cypress sram, lab stock na na u07 1 ds3/e3 sct, 11x11 csbga, 100 pin maxim ds3170 u08 1 t1/e1/j1 xcvr 100p qfp 0-70c maxim ds2156l ub01, ub02, ub03, ub04 4 ic, linear reg 1.5w, 3.3v or adj, 1a, 16tssop-ep maxim max1793eue-33 ub05 1 8-pin umax soic 1.8v or adj maxim max1792eua18 ub06 1 spi serial eeprom 2m 8 pin soic 2.7v to 3.6v atmel at25f2048n-10su-2.7 ub07, ub12 , ub14 3 high speed buffer fairchild nc7sz86 ub08 1 dual rs-232 transceivers with 3.3v/5v internal capacitors maxim na ub09 1 ic, ldo regulator with reset,1.20v output 300 ma, 6 pin sot23 maxim max1963ezt120-t ub10 1 synchronous dram, 1megx32x4 banks, tsop 86 pin micron mt48lc4m32b2tg-7 ub11 1 microprocessor voltage monitor, 3.08v reset, 4pin sot143 maxim max811teus-t xb01 1 xtal low profile 8.0mhz ecl ec1-8.000m y01 1 spi serial eeprom 16k 8 pin dip 2.7v socket only atmel at25160a-10pi-2.7 yb01 1 xtal, low profile, 6.00 mhz pletronics lp49-26-6.00m yb02 1 oscillator, crystal clock, 3.3v socket saronix na yb03 1 oscillator, crystal clock, 3.3v - 100.000 mhz saronix nth089a3-100.0000 yb04 1 oscillator, crystal clock, 3.3v - 2.048 mhz saronix nth039a3-2.0480 yb05 1 oscillator, crystal clock, 3.3v - 44.736 mhz saronix nth089aa3-44.736 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 14 of 15 10. schematics the DS33Z11DK schematics are featured in the following pages. as this is a hierarchal schematic some explanation is in order. the main board is composed of three hierarchal blocks: the processor block, the ds33z11 block, and an ethernet block inside the ds33z11 block, which is a nested hierarchy block. the serial card consists of two hierarchy blocks, one for each of the ds2155, and ds3170. these bloc ks are connected by jumpers to the ds33z11. all signals inside a hierarchy block are local, with exception for v cc and ground. in-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. from here blocks are wired together as if they were ordina ry components. the system diagram is shown again below, with schematic page numbers given for each functional block. p block page 2 symbol schematic pages 13-19 ds33z11 block page 2. symbol schematic pages 03-07 cpld mux and selection jumpers ds2155 block page 2 symbol schematic pages 10-11 ds3170 block page 2 symbol schematic pages 12-12 ethernet phy page 6 symbol schematic pages 08-09 downloaded from: http:///
_______________________________________________________________________________ DS33Z11DK rev: 080508 15 of 34 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the ci rcuitry and specifications wi thout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products. 11. revision history revision date description pages changed 031405 initial DS33Z11DK data sheet release. 042205 updated basic ds33z11 initialization section; added step to quick setup #1 section; updated table 2. 9, 11, 12 110106 updated schematics. 15C39 080508 reformatted data sheet to conform to newer template style; updated various sections to include the DS33Z11DK01a0 revision. all downloaded from: http:///
all hierarchy block names end in _dn. pins on hierarchy blocks do not have pin numbers (but pins on s ymbols do). signals inside a hierarchy block are local to that block the signal _temp_ in block_a_dn is different than _temp_ in b lock_b_dn. page numbers (bottom right) are listed by both the page numbe r in the block, and by the page number within the entire design cross reference indicators are referenceing a given net to o ther pages in the design (page number given is according to entire design, not the cur rent block) page 13-19: microprocessor, reset control and power supply notes: contents: DS33Z11DK02a0 ds33z11 design kit page 02: hierarchy blocks for ds33z11, ds2155, ds3170, micr oprocessor page 12: t3e3 wan page 10-11: t1e1 wan page 08-09: ethernet phy page 6: hierarchy block for ethernet phy page 03-07: ds33z11 and ethernet phy steve scully 1/2(block) DS33Z11DK02a0 02/06/2007 1/19(total) printed fri jun 20 10:05:53 2008 block name: _ztopdn_. page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///
pages 12-12 pages 13-19 pages 10-11 hierarchical block hierarchical block pages 03-07 hierarchical block wan_int ub14 cs_te1 rd jp22 te3_rser dat<7..0> addr<9..0> int_z11 reset_sys i61 reset_sys dat<7..0> cs_te3 rd wr wan_int wan_int addr<12..0> int4 cs_te3 cs_x4 cs_x5 rd wr dat<7..0> int5 cs_te1 z11_rden 30 30 10k addr<7..0> cs_z11 int_z11 wr wr rd cs_z11 rb36 rb37 jp23 tp06 tp05 rpb12 reset_sys ub12 te1_rgapclk te1_rser reset_sys addr<8..0> buffer dat<7..0> te1_tgapclk inverter jp21 jp20 te1_tser 30 z11_tclki 30 rb40 rb39 rb38 z11_tden z11_tser z11_rser z11_rclki te3_tser te3_tgapclk te3_rgapclk 30 steve scully 2/2(block) DS33Z11DK02a0 02/06/2007 2/19(total) block name: _ztopdn_. 1 3 2 1 3 2 1 3 2 4 1 1 3 2 1 1 3 1 2 5 6 7 8 4 4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 _motprocrescard_dn microprocessor hierarchical block int2 int3 int4 int5 spi_mosi spi_cs d_dut<7..0> wr_dut rd_dut cs_x5 cs_x4 cs_x3 a_dut_<12..0> reset_sys cs_x2 cs_x1 spi_miso spi_sck v3_3 _te3wan_dn addr<8..0> jtms jtclk jtdi jtdo jtrst t3_int wr rd cs dat<7..0> te3_rser te3_tser te3_rgclk te3_tgclk reset_sys nc7sz86_u _te1wan_dn jtms jtclk jtdi jtdo jtrst t1_int dat<7..0> cs wr rd reset_ah addr<7..0> rser tser tgapclk rgapclk nc7sz86_u _z11andlan_dn reset_sys tden rden tser rser tclki cs rd rclki wr addr<9..0> dat<7..0> int downloaded from: http:///
beginning of ds33z11 hierarchy block hw mode pins are outputs from z module to proc led+tp proc (fpga) automaticaly implements bus mode (output) (input) ds33z11 block name: _z11andlan_dn. parent block: \_ztopdn_\ DS33Z11DK02a0 jtdo tclki 1/5(block) steve scully 3/19(total) 02/06/2007 zspisck zspics zmiso zmosi 2.7v zaddr1 dat<7..0> red rpb07 j07 rpb06 rp05 jp18 jp17 jp16 u03 rb32 rb29 ds10 ub07 tp01 ds09 rb26 tp02 rb30 rb28 ref_clko ref_clk txd1 txd0 tx_clk rx_clk rxd1 rxd0 rxd2 6 0 rser int rd jtdo cs zspics wr reset_sys hwmode modec0 modec1 dcedtes rmiimiis fullds h10s afcs scanen scanmod ckpha rclki rxdv rxd3 jtdi rden tden zmosi zaddr0 zaddr1 zspisck zmiso zaddr2 jtclk jtrst jtms rx_crs 2 addr<9..0> 330 zaddr0 2.2k zaddr2 mdc tx_en 330 tser 30 red 3 int addr<9..0> 2 1 0 10k 10k 330 30 30 mdio jtrst jtclk jtms jtdi 9 8 7 5 4 34 6 57 1 buffer rx_err col_det txd3 txd2 rpb03 y01 1 2 4 1 1 2 1 3 2 1 3 2 1 3 2 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 1 6 2 87 34 5 1 9 57 3 4 26 10 8 b11 e10 e9 a10 b12 c8 e13 c7 f7 e6 d4 a2 a3 b3 a4 c3 b4 a6 a7 b6 f1 c2 b7 b1 a1 b2 c12 c5 c6 a5 b5 f5 h2 e4 d9 c9 b13 c11 a11 d10 g2 f6 e8 e7 c10 b10 a9 c4 a13 d7 d6 d5 d8 e2 b8 c1 e5 c13 e1 f3 d11 f2 d13 a8 b9 h1 jtag line io micro port/spi master port mii/rmii ports ds33z11_u3 rser txd<0> tx_clk ref_clk tser rxd<2> int* rd*/ds* mdio jtdo cs* spi_cs* wr*/rw* rst* hwmode modec<0> modec<1> dcedtes rmiimiis fullds h10s afcs scan/en scan/mode ckpha rclki rxdv rxd<3> rxd<1> col_det txd<1> txd<2> jtdi rden/rbsync tden/tbsync d<3> d<0>/mosi d<7> d<6> mdc a<3> a<0> a<1> d<5> a<4> tclki d<4> d<2>/spick d<1>/miso a<9> a<7> a<8> a<6> a<5> a<2> jtclk jtrst jtms qovf ref_clko rx_crs/crs_dv rx_err rx_clk txd<3> tx_en rxd<0> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo in in at25160a_u si gnd wp* hold* vcc so sck cs* out io in in in out in in in in io v3_3 v3_3 v3_3 nc7sz86_u downloaded from: http:///
z41rsync 26 25 23 24 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i228 nc_pinf9 z41tsync v1_8zchip ds33z11 na 11 10 9 8 7 6 5 4 3 2 1 0 sd_we sd_cas sd_cs sd_dqm3 sd_dqm2 sd_dqm1 sd_dqm0 sd_ba1 sd_ba0 sd_a<11..0> 27 28 29 31 30 sd_dq<31..0> sd_clko sd_clki sd_ras tp04 tpb02 tpb01 u03 block name: _z11andlan_dn. parent block: \_ztopdn_\ DS33Z11DK02a0 steve scully 2/5(block) 02/06/2007 4/19(total) 1 1 1 f4 g6 h6 f10 l3 e11 e12 d12 m13 n2 m2 l2 n1 m1 k1 j1 j2 h3 m3 j3 l4 n4 n3 l1 k2 j12 m5 m7 m8 n8 g4 m10 m9 g13 k6 n5 l6 e3 d2 m12 h11 m11 n13 n11 l13 n12 k13 j13 m4 h4 m6 n7 l12 l5 l7 l8 l9 n9 g5 d3 h5 h10 k12 f12 f13 j10 j8 j9 k8 k7 j11 j6 f8 h7 j7 h13 h12 g12 f11 g11 l10 a12 k9 h9 k5 j5 k10 k3 f9 g1 g3 d1 h8 k11 l11 n10 g8 g7 g9 g10 n6 k4 j4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 pwr/gnd sdram controller system ds33z11_u3 4vdd1.8 5vdd1.8 sdmask<0> 5vdd3.3 4vdd3.3 2vdd3.3 3vdd3.3 sda<1> sda<2> sda<3> 9vdd3.3 vss0 nc3 nc2 nc1 vss1 vss2 vss4 vss5 10vdd3.3 vss13 vss18 sdata<31> sdata<30> sdata<29> sdata<28> sdata<27> sdata<26> vss8 8vdd3.3 vss3 vss6 vss7 vss9 vss11 vss12 vss10 vss14 vss17 vss16 vss15 11vdd3.3 6vdd3.3 0vdd1.8 0vdd3.3 sda<0> sda<6> sda<5> sda<4> sda<7> 12vdd1.8 sba<1> sba<0> scas* swe* sdata<24> sdata<23> sdata<22> sdata<21> sdata<20> sdata<19> sdata<18> sdata<17> sdata<16> 1vdd1.8 2vdd1.8 sdcs* sdclko sras* sysclki sdmask<3> sdmask<2> sdmask<1> sda<11> sda<10> sda<9> sda<8> sdata<25> sdata<14> sdata<15> sdata<6> sdata<5> sdata<7> sdata<8> sdata<9> sdata<10> sdata<12> sdata<11> sdata<13> sdata<0> sdata<2> sdata<1> sdata<3> sdata<4> 11vdd1.8 10vdd1.8 9vdd1.8 8vdd1.8 6vdd1.8 7vdd1.8 7vdd3.3 1vdd3.3 3vdd1.8 v3_3 downloaded from: http:///
from z11 sysclko synchronous dram mt48lc4m32b2 - 1 meg x 32 x 4 banks 09 10 11 0 1 31 30 2 1 34 5 7 68 9 10 11 12 2 13 14 15 16 17 18 19 20 21 3 22 23 24 25 26 27 28 29 45 6 7 8 sd_dq<31..0> sd_ba1 sd_ba0 sd_dqm3 sd_clko sd_dqm1 sd_dqm0 sd_ras sd_cas sd_we sd_cs sd_a<11..0> sd_dqm2 ub10 5/19(total) 02/06/2007 3/5(block) steve scully DS33Z11DK02a0 block name: _z11andlan_dn. parent block: \_ztopdn_\ 43 29 55 3 68 20 67 18 17 16 19 71 28 59 22 23 25 26 60 27 61 63 62 65 64 66 24 21 10 11 13 74 76 77 79 80 83 82 85 31 33 34 37 36 39 42 40 47 45 48 50 51 53 49 41 8 15 1 57 42 54 56 84 52 78 46 32 38 6 12 72 86 44 58 75 81 35 9 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 mt48lc4m32b2_tsop_u vddq2 vddq3 vddq8 vddq7 vss2 vss1 vss4 vss3 vssq2 vssq1 vssq4 vssq3 vssq5 vssq7 vssq6 vssq8 dq<31> dq<30> dq<0> dq<1> dq<3> dq<2> vdd1 vdd2 dq<4> vddq4 vddq5 dq<29> dq<28> dq<27> dq<26> dq<24> dq<25> dq<22> dq<23> dq<21> dq<19> dq<20> dq<18> dq<17> dq<16> dq<15> dq<13> dq<14> dq<12> dq<11> dq<10> dq<9> dq<8> dq<7> dq<6> dq<5> a<11> a<10> a<9> a<7> a<8> a<5> a<6> a<4> a<2> a<3> a<1> a<0> ba<1> ba<0> dqm<3> dqm<2> dqm<1> ras* dqm<0> we* cas* cke cs* clk vddq1 vddq6 vdd3 vdd4 v3_3 downloaded from: http:///
pages 08-09 hierarchical block 25.0 mhz socket sd_clki r07 yb03 reset_sys 30 mdc tx_en tx_clk txd0 txd1 mdio txd2 rx_clk rxd0 rxd1 rxd2 rxd3 rx_crs rx_err rxdv col_det txd3 30 100.000mhz_3.3v ref_clk 0.0 ref_clko r06 mii_clk r08 yb02 4/5(block) block name: _z11andlan_dn. parent block: \_ztopdn_\ steve scully 02/06/2007 DS33Z11DK02a0 6/19(total) 1 8 4 5 1 8 4 5 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 vcc 1 osc gnd out v3_3 _dp83848_wan_dn reset_sys phy_clk25m txd_3_sni_mode col_phyad0 rx_dv_mii_mode rx_er_mdix_en crs_dv_led_cfg rxd_3_phyad4 rxd_2_phyad3 rxd_1_phyad2 rxd_0_phyad1 rx_clk txd2 mdio txd1 txd0 tx_clk tx_en mdc v3_3 vcc 1 osc gnd out in downloaded from: http:///
high mode (shown below signal) results in: motorola non-mux, mii, full duplex, 100 mbit, auto-flow con trol low high low low low low low low high low config switches for z11 end of ds33z11 hierarchy block v1_8zchip 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf v1_8zchip 10uf 4.7uf .01uf .01uf 1uf 4.7uf 10uf 1uf 4.7uf hwmode 2.2k modec1 2.2k rmiimiis 2.2k h10s 2.2k scanen 2.2k ckpha 2.2k scanmod 2.2k afcs 2.2k fullds 2.2k dcedtes 2.2k modec0 2.2k jp06 jp07 jp10 jp19 jp05 jp09 jp04 jp13 jp15 jp11 jp08 cb18 c12 2 1 cb15 c14 2 1 ub05 c16 cb21 c13 1 2 cb17 cb49 c30 cb36 c31 cb52 cb64 c23 c29 c27 cb46 cb40 cb60 cb39 cb63 DS33Z11DK02a0 block name: _z11andlan_dn. parent block: \_ztopdn_\ steve scully 5/5(block) 02/06/2007 7/19(total) r7 r8 r9 r15 r16 r1 r2 r3 r4 r5 r6 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 34 2 85 6 7 1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1792 in out set gnd out in shdn rst v3_3 v3_3 downloaded from: http:///
resistors for td+-/rd+- rbias resistor must each pfbin pin requires 0.1uf cap near pin should be placed close to phy be placed close to pin beginning of phy hierarchy block 2.2k 2.2k 4.87k td_p td_n rd_p rd_n reset_sys led_act_col_an_en 0.1uf 4.7uf 0.1uf an_v3_3 .1uf 0.1uf 0.1uf 50 .1uf 0.1uf .01uf 0.0 4.7uf 4.7uf 4.7uf .01uf 0.1uf .01uf 0.1uf 2.2k 30 30 30 30 2.2k rxd_3_phyad4 rxd_2_phyad3 tx_clk rxd_1_phyad2 rx_clk crs_dv_led_cfg rx_er_mdix_en col_phyad0 rxd_0_phyad1 rx_dv_mii_mode an_v3_3 pfbout txd2 txd1 tx_en pwr_dwn rbias an_v3_3 phy_clk25m mdio mdc led_speed_an1 led_link_an0 txd_3_sni_mode txd0 cb16 c19 cb04 cb06 cb07 cb23 u01 rb07 cb14 cb32 cb33 rp03 r04 r03 rp02 rb06 rb16 rp04 r01 rb05 cb09 cb20 cb10 cb26 cb11 cb05 c17 rp01 steve scully DS33Z11DK02a0 02/06/2007 1/2(block) 8/19(total) printed fri jun 20 10:04:01 2008 block name: _dp83848_wan_dn. parent block: \_z11andlan_d n\ 2 1 35 47 36 15 19 11 12 6 5 4 3 2 1 45 46 7 44 17 16 20 24 21 18 23 37 22 32 25 34 48 39 38 41 40 42 43 30 31 27 26 28 33 29 13 14 10 89 2 1 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 2 1 2 1 2 1 2 1 2 1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 io v3_3 v3_3 v3_3 dp83848 tdo tck tms rd + rd - reset_n x2 led_link/an0 led_act/col/an_en led_speed/an1 mdc mdio rxd_0/phyad1 col/phyad0 crs/crs_dv/led_cfg rx_er/mdix_en rx_clk rx_dv/mii_mode iovdd33 x1 25mhz_out iovdd33 avdd33 pfbin2 pfbout pfbin1 reserved rbias reserved td - td + rxd_1/phyad2 pwr_down/int rxd_3/phyad4 rxd_2/phyad3 tx_clk tx_en txd_0 txd_1 txd_2 txd_3/sni_mode tdi trst# agnd agnd dgnd iognd iognd in in v3_3 in downloaded from: http:///
allow use of an external phy card if desired. placement shoul d allow 0.2 between connectors. testpoints (shown above) must be placed the same for each por t to placement note: strap options here do not follow the dp83484 datasheet (some pins have a 2.2k+330 strap resistor instead of 2.2k) low for mii, high for rmii caps for xfrm center tap should be placed close to xfrm phy mdio address (0x01) end of phy hierarchy block 330 1 1 1 green 1 txd1 txd0 txd2 tx_clk tx_en td_n an_en rx_dv_mii_mode rx_er_mdix_en rx_clk crs_dv_led_cfg col_phyad0 rxd_3_phyad4 rxd_2_phyad3 rxd_0_phyad1 rxd_1_phyad2 2.2k .1uf sym_1 rd_p 1 .1uf td_p rd_n 2.2k rx_er_mdix_en 2.2k 2.2k led_act_col_an_en txd_3_sni_mode red red txd_3_sni_mode rx_dv_mii_mode 1 an0 amber amber an1 green a0402_5pct exb-n8v222jx 2.2k i99 led_speed_an1 led_link_an0 rxd_0_phyad1 rxd_3_phyad4 rxd_2_phyad3 rxd_1_phyad2 2.2k col_phyad0 j02 cb08 cb13 j05 j06 jp03 jp02 ds06 ds05 jp01 ds01 ds04 ds03 ds02 jp14 jp12 rpb01 rpb01 rpb01 rpb01 rpb05 rpb02 rpb04 02/06/2007 2/2(block) steve scully 9/19(total) DS33Z11DK02a0 block name: _dp83848_wan_dn. parent block: \_z11andlan_d n\ 9 28 6 3 4 10 1 5 6 5 4 9 7 3 10 8 1 2 6 5 4 9 7 3 10 8 1 2 1 3 2 1 3 2 1 2 1 2 1 3 2 1 2 1 2 1 2 1 2 1 3 2 1 3 2 8 1 7 2 6 3 5 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 v3_3 v3_3 v3_3 v3_3 6 10 8 4 1 2 35 7 9 conn_10p v3_3 out out out out 6 10 8 4 1 2 35 7 9 conn_10p out out out out in out out in in in in v3_3 v3_3 conn_hfj11_2450_u j1 j2 j3 j6 j4,5 j7,8 p5 p1 sh2 p4 p3 p6 p8 p2 sh1 downloaded from: http:///
/ te1 single wan block beginning of t1e1 hierarchy block 30 0.0 0.0 tring55 ttip55 1uf 0.0 0.0 61.9 61.9 .1uf rring55 rtip55 j14 t01 c44 r10 r11 j16 t01 r14 r12 rb44 rb46 cb95 r13 j15 block name: _te1wan_dn. parent block: \_ztopdn_\ steve scully 02/06/2007 1/2(block) 10/19(total) DS33Z11DK02a0 4 3 2 1 14 16 15 2 1 2 1 2 1 2 1 1 2 1 4 7 2 3 6 8 5 1 2 87 6 5 9 11 10 2 1 2 1 2 1 1 2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 g s 1:1 1:0.8 g s conn_rj48 e h f c b g d a 1:1 1:0.8 downloaded from: http:///
end of t1e1 hierarchy block tsync55 rclki55 bts55 rsync55 i95 10k rsysclk55 i98 10k 10k i97 mux55 tclki55 tnegi55 tsysclk55 10k i96 tposi55 rposi55 esibrd55 rnegi55 10k i93 jtdi 3 10k red 330 72 1 07 3 40 2 65 6 5 dat<7..0> tgapclk 1 tdata55 jtclk addr<7..0> 4 rgapclk jtms jtrst jtclk jtdo tsig55 tssync55 tlink55 liuc55 i94 10k rtip55 rsync55 rgapclk rring55 wr rd reset_ah mclk55 rclki55 rsysclk55 tnegi55 rnegi55 rlos_lotc55 jtdi jtms esibrd55 tser rser mux55 bts55 tposi55 jtdo jtrst tclki55 tring55 tsync55 tgapclk tsig55 rposi55 tlink55 tclki tssync55 cs t1_int liuc55 ttip55 tsysclk55 tclki 30 2.048mhz_3.3v ds13 rb52 u08 yb04 rb51 rb48 rp08 rpb19 rpb21 rpb20 rpb18 rpb22 DS33Z11DK02a0 02/06/2007 steve scully 2/2(block) 11/19(total) block name: _te1wan_dn. parent block: \_ztopdn_\ 16 82 78 72 71 83 98 92 79 57 68 24 17 28 77 74 14 93 21 89 90 91 88 100 39 87 99 4 7 69 70 85 27 22 76 47 26 20 95 94 55 11 60 45 61 44 31 97 38 30 19 10 5 42 41 40 43 32 81 37 53 48 49 86 18 35 46 50 52 33 75 56 67 66 25 6 12 29 13 34 51 65 64 63 62 73 96 3 80 84 36 54 89 15 23 59 58 8 4 5 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 43 1 2 5 6 7 8 43 1 2 5 6 7 8 43 1 2 5 6 7 8 43 1 2 5 6 7 8 4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 in in in io io in v3_3 vcc 1 osc gnd out tqfp ds2156 d/ad<2> d/ad<3> uop3 uop2 uop1 uop0 esibs<1> esibs<0> dvss4 dvss3 bpclk rmsync ale/as/a<7> d/ad<4> d/ad<5> d/ad<6> d/ad<7> tsysclk tlclk 8xclk ttip liuc rcl int* a<0> a<1> d/ad<0> cs* tchblk rchblk tssync tdata tclk tlink rvdd rposi teso tsig tchclk tsync dvdd3 tring tposo tclki tclko tnego jtrst jtdo rvss1 tvss tposi rfsync tvdd dvdd1 dvdd2 dvss1 dvss2 bts mux rsig rser rvss2 nc1 tser esibrd xtald nc2 rdata a<4> a<3> jtms jtdi jtclk rlos/lotc rnegi tnegi rsysclk rclki rposo rnego rclko mclk rsigf tstrst rd/ds* wr/rw* nc3 rring rvss3 a<2> d/ad<1> rlclk rchclk rsync dvdd4 a<5> a<6> rlink rclk rtip out v3_3 in in in in in out in io io v3_3 downloaded from: http:///
jtag testpoints no tpdeno? hiz,test,ale ds33z11 te3 wan block (ds3170 sct, transformers and connectors) beginning/end of t3e3 hierarchy block DS33Z11DK02a0 steve scully 02/06/2007 1/1(block) 12/19(total) block name: _te3wan_dn. parent block: \_ztopdn_\ tpb03 te3_tsofo_tden te3_rsofo_rden 2.2k 2.2k mode t3_int 30 30 te3_rgclk addr<8..0> jtrst jtdo jtdi jtclk jtms 10k t3mclk cs width te3_rser te3_tgclk te3_tser te3_rxp rd wr 7 rref1 tref1 75 ohm 2p te3_tclki erj-3geyj300v smt0603_5pct 30 te3_tclki erj-3geyj300v smt0603_5pct 30 te3_txn 10k dat<7..0> 08 te3_rxn 1 332 te3_txp 332 6 5 4 1 0 7 6 5 24 red 330 2 44.736mhz_3.3v 3 i85 10k jtrst jtdo jtdi jtclk jtms reset_sys 3 75 ohm 2p t3mclk yb05 u07 t02 rb50 j17 t02 rb49 j18 rb43 ds12 tpb04 rpb17 rpb16 rb41 rb42 rp07 1 8 4 5 c2 b2 c5 f4 e3 b7 j7 h3 g3 a3 j2 k2 k3 j4 g4 b3 e9 d9 e1 e2 f1 f2 a8 f10 f9 a4 c7 e10 d7 g9 b6 c9 c10 a9 b10 b9 c8 c6 a6 b8 f6 g5 d3 e6 b4 f5 d4 g7 f7 e7 e8 g1 d2 e4 b5 a2 a10 g10 k6 k1 c1 j1 d8 h2 f3 c3 a1 a5 c4 d5 e5 b1 d1 a7 g2 h1 d6 h10 g8 h8 h9 j10 j9 g6 j8 k8 h7 h6 k7 j6 k9 h5 j5 j3 f8 k5 k4 d10 k10 h4 rb53 28 27 6 5 1 2 26 25 8 7 rb54 r18 r17 1 2 1 2 1 1 3 1 2 5 6 7 8 43 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in v3_3 out in in in in in in in v3_3 v3_3 in g s v3_3 out 2:1 g s 2:1 v3_3 ds3170_bga_u a<6> vdd4 vdd5 vdd3 a<0>/bswap rohsof a<4> d<0>/spi_miso a<8> d<1>/spi_mosi d<2>/spi_sclk d<4> d<3> d<6>/spi_cpha d<7>/spi_cpol d<8> d<9> d<10> d<11> d<13> d<12> d<15> d<14> nc refclk clko vdd6 vdd2 vdd1 jtrst* jtdo jtdi jtclk cs* spi mode width int* rdy* vss1 vss2 vss3 vss4 vss5 vss6 avssr avsst avssj avssc gpio<1> gpio<2> gpio<3> gpio<4> gpio<8> test* hiz* rst* gpio<7> gpio<6> gpio<5> rsofo/rden rclko/rgclk rser tsofo/tden tclko/tgclk tser tsofi tclki rohclk roh tohsof tohclk tohen toh rxp rneg/rlcv rpos/rdat rlclk txn2 txn1 txp2 txp1 tneg tpos/tdat jtms ale a<7> a<5> a<2> a<1> rxn avddc a<3> d<5>/spi_swap tlclk avddj avddt avddr rd*/ds* wr*/rw in io in vcc 1 osc gnd out v3_3 out in downloaded from: http:///
beginning of processor hierarchy block 13/19(total) printed fri jun 20 10:02:20 2008 block name: _motprocrescard_dn. parent block: \_ztopdn_\ steve scully 02/06/2007 1/7(block) DS33Z11DK02a0 rb34 u04 u04 1 cb70 user_led1 user_led2 kit_status run_kit_usr pqa0 pqa1 pqa3 pqa4 pqb0 pqb1 pqb2 pqb3 eb0 eb1 eb2 eb3 icoc23 icoc22 icoc21 icoc20 icoc13 icoc12 icoc11 icoc10 sci2_out sci2_in sci1_out sci1_in test osc_mcu once_tclk once_trst_b spi_cs cs3 tc1 once_tdi 2107_tdo cse1 tim_16h_8l tc2 cse0 cs1 cs2 once_de_b spi_sck proc_reset_out cpuclk_out cs0 once_tms int2 yco spi_mosi spi_miso xtal int4 int3 ta rcon oe vrh tea flash_vpp rw 31 10 4 27 26 17 25 20 22 13 12 11 10 8 97 6 5 3 21 4 1 0 .1uf 20 0 2 3 5 30 29 19 28 24 23 6 7 8 9 21 18 19 17 18 16 13 12 11 16 15 14 gnd pa<22..0> 2 1 22 15 14 pd<31..0> 0.0 vddsyn reset_sys 45 9 19 17 20 21 22 25 27 30 31 34 35 16 15 12 10 7 5 4 3 2 1 36 37 38 39 40 41 42 43 46 48 51 114 73 126 140 127 76 64 44 32 18 8 50 49 47 29 28 26 24 23 13 11 6 139 137 136 134 132 131 122 121 119 117 116 144 14 112 59 65 33 123 141 129 77 87 115 74 103 102 92 113 95 97 99 69 68 82 84 75 79 124 91 90 80 71 138 86 118 128 120 93 143 83 85 62 67 98 100 101 104 105 106 88 96 60 135 133 78 81 110 111 109 108 107 94 142 130 125 53 52 55 54 58 57 56 72 63 61 66 89 70 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out out in out mmc2107 control rxd1 int7* txd2 icoc10 test int1* icoc13 icoc12 icoc11 icoc21 icoc20 icoc23 icoc22 extal tclk trst* ss* pqb0 pqa4 pqa3 pqa0 pqa1 cs3* tc1 tdi tdo cse1 eb3* int6* pqb1 pqb2 pqb3 eb0* eb1* eb2* tc2 cse0 cs1* cs2* de* sck rstout* clkout reset* cs0* tms int0* yc0 mosi miso xtal int3* int2* int5* int4 rxd2 txd1 mmc2107 port ta* shs* oe* vrh vstby tea* vddh vddf vdda vpp vdd6 vdd7 vdd8 vddsyn vdd3 vdd5 rw vrl a8 d31 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a7 a6 a5 a4 a3 a2 a1 a0 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vsssyn vssf vssa d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 vdd2 vdd1 vdd4 v3_3 downloaded from: http:///
xtal w/ pll boot internal full drive internal flash enable master mode boot intern/extern when set for d18 has a 10k load to gnd reset configuration 10k pd<21> pd<17> pd<26> pd<16> rcon pd<19> pd<18> 9 8 7 6 5 4 3 2 1 17 16 15 14 12 11 10 pd<31..24> 18 23 cs0 eb1 oe cy62128v pa<17..1> cs0 eb0 oe 17 15 1 2 3 4 5 6 7 8 16 14 13 12 11 10 9 22 31 30 29 28 27 26 25 21 24 19 20 17 16 pa<17..1> 13 pd<28> pd<23> pd<22> 10k 10k int4 int5 int3 cs_x4 cs_x5 cs_x1 cs_x3 cs_x2 int2 wr_dut rd_dut pd<23..16> cy62128v reset_sys u06 ub13 rpb10 rpb13 rpb08 a_dut_<12..0> d_dut<7..0> block name: _motprocrescard_dn. parent block: \_ztopdn_\ 02/06/2007 steve scully DS33Z11DK02a0 14/19(total) 2/7(block) 3 1 2 5 6 7 8 43 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 21 20 19 18 17 15 14 13 27 26 23 25 4 28 3 31 2 32 16 24 29 1 12 11 10 9 8 7 6 5 30 22 21 20 19 18 17 15 14 13 27 26 23 25 4 28 3 31 2 32 16 24 29 1 12 11 10 9 8 7 6 5 30 22 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 cy62128v ce1* ce2 a7 a6 a5 a4 a3 a2 a1 a0 n_c we* oe* gnd vcc a16 a15 a14 a13 a12 a11 a10 a9 a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 cy62128v ce1* ce2 a7 a6 a5 a4 a3 a2 a1 a0 n_c we* oe* gnd vcc a16 a15 a14 a13 a12 a11 a10 a9 a8 io0 io1 io2 io3 io4 io5 io6 io7 io out out out in out out out out out out in in in v3_3 downloaded from: http:///
align key but do not populate place pads for cap 10uf 10uf osc_mcu xtal 8.0mhz usb 330 kit_status green 30 10k 7 6 5 4 3 2 1 0 1.0m 10k prt1_in prt1_out sci1_in sci1_out prt1_in prt1_out 10k con14p flash_vpp 2107_tdo once_tdi once_tms once_trst_b 330 once_de_b 22pf .1uf .01uf once_tclk reset_sys si_wuusb wrusb d_dut<7..0> 30 6.00mhz 22pf rd_usb txe_usb rxf_usb pwren_usb 30 2.2k j13 ub08 j10 r09 1 2 1 xb01 j11 rpb14 rpb11 c09 1 2 1 c08 1 2 1 c10 u02 yb01 c11 rb21 1 2 1 rb23 1 2 1 rb18 j03 rb19 1 2 1 rb24 1 2 1 ds07 r02 cb28 cb22 3/7(block) 02/06/2007 steve scully DS33Z11DK02a0 block name: _motprocrescard_dn. parent block: \_ztopdn_\ 15/19(total) 13 9 7 5 11 3 1 10 12 8 6 4 14 2 20 1 8 45 6 7 9 10 11 12 13 14 15 16 17 18 19 3 2 9 5 4 2 1 3 67 8 2 1 2 1 3 1 2 5 6 7 8 4 3 1 2 5 6 7 8 4 r05 2 1 5 18 20 23 22 21 25 24 14 15 30 26 13 29 17 9 31 2 1 32 4 3 7 8 19 27 28 16 6 10 12 11 2 1 2 1 2 1 1 23 4 5 1 2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v5_0 v3_3 gnd dat- vdd dat+ usb ft245bm_u si_wu rxf# pwren# 3v3out rd# xtout xtin d6 usbdm usbdp vcc1 reset# eecs eesk eedata test gnd1 gnd2 agnd vccio vcc2 avcc wr txe# d1 d0 d4 d3 d2 d5 d7 rstout# v5_0 v3_3 v3_3 v5_0 v3_3 v3_3 conn_db9p h g f c a b de j max3233e invalid* t2in t2out gnd v- c2- c2+ c1- c1+ v+2 v+1 forceoff* vcc t1out r1out forceon t1in r1in r2out r2in v3_3 con14p downloaded from: http:///
mem_sck must be at pin77 for tqfp144 connect a different processor this allows the user to the address databuss of the fpga. jumper pins 12+14 to tristate signals have pulldowns inside fpga driver / callbacks / looptime note: j04 pins 1,3,5,7,9 were left unconnected they are now connected to vcc by rework wire enable_driver_h jmp04p8 jmp04p10 enable_callbacks_h loop_sourcetime j04 i147 si_wuusb pwren_usb int2 tristate_ad_bus cs2 eb0 enable_driver_h cs_x1 cs_x2 a_dut_<12..0> 12 int2 enable_callbacks_h mem_sck tristate_ad_bus int3 nopop mem_so 1 mem_cs mem_si wr_dut 0 d_dut<7..0> rd_dut rxf_usb txe_usb rd_usb rd_dut wr_dut cs_x1 cs_x3 cs_x2 cs_x4 10k 1 2 0 3 4 5 6 7 8 nopop 7 6 5 4 23 int2 int4 int5 int3 10k wrusb 330 d_dut<7..0> 12 11 10 9 8 7 6 5 4 3 2 1 0 a_dut_<12..0> 16 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 27 29 31 30 28 26 25 24 22 21 20 19 18 17 16 pa<16..0> 76 5 4 3 2 1 0 23 pd<31..16> 0.0 97_io int5 oe rw cs0 cs1 cpuclk_out cs_x4 cs_x3 cs_x5 misc_led u05 rb25 rb22 rpb09 rb35 j08 j09 ds08 4 loop_sourcetime jmp04p10 jmp04p8 eb1 block name: _motprocrescard_dn. parent block: \_ztopdn_\ 16/19(total) 4/7(block) 02/06/2007 steve scully DS33Z11DK02a0 3 1 2 5 6 7 8 4 2 1 24 8 6 3 1 9 11 13 10 57 14 12 24 8 6 3 1 9 11 13 10 57 14 12 6 5 4 9 7 3 10 8 1 2 85 87 88 127 77 8 75 74 76 78 79 82 83 100 101 102 103 105 104 107 106 124 123 122 138 137 121 119 118 120 116 115 114 113 112 111 67 5 4 3 2 69 70 68 66 64 61 32 39 41 42 43 45 46 47 48 50 49 53 56 34 35 33 30 31 29 23 22 21 20 57 62 65 67 40 141 142 135 60 59 58 51 140 139 25 26 27 134 86 81 131 132 133 129 130 9 1 2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 bank 3 lfec_t144_u bank 0 i/o port bank 6 bank 4 bank 5 bank 1 bank 2 input pll pll input pll input bank 7 input pll input pll pll input pl9b/pclkc7_0 pt16b/vref1_0 pt17a/pclkt0_0 pt15a pt15b pt16a/vref2_0 pr14a/rlm0_pllt_fb_a pr12a/dout/cso* pt14b pl14a pl13b pl13a pt12b pt12a pb17a/pclkt5_0 pb19a/vref1_4 pb19b/cs* pb20a/vref2_4 pt14a/tdqs14 pt10a pt10b pb10b pb23a pb22a/bdqs22 pb21a/d2/spid5 pb18b/cs1* pl11a/llm0_pllt_in_a pl11b/llm0_pllc_in_a pl12a/llm0_pllt_fb_a pl12b/llm0_pllc_fb_a pl14b pl15b pl15a/ldqs15 pl16b pl18b/vref2_6 pl18a/vref1_6 pb18a/write* pb17b/pclkc5_0 pb16a/vref2_5 pb16b/vref1_5 pb15b pb15a pb14b pb14a/bdqs14 pb13b pb11b pb11a pb10a pl16a pb20b/d0/spid7 pb21b/d1/spid6 pb22b/d3/spid4 pb23b/d4/spid3 pb25b/d6/spid1 pb24b/d5/spid2 pl2a/vref2_7 pl2b/vref1_7 pl7a pl7b pl8b pl8a pt25b pt25a pt23a pt22b pt22a/tdqs22 pt21b pt20a pt21a pt20b pt19b/vref2_1 pt13b pt13a pt19a/vref1_1 pt18b pt18a pr2b/vref1_2 pr2a/vref2_2 pr7b pr7a pr8a pr8b pr9a/pclkt2_0 pr9b/pclkc2_0 pr13a/rlm0_pllt_in_a pr13b/rlm0_pllc_in_a pr14b/rlm0_pllc_fb_a pr15a/rdqs15 pr16a pr18a/vref1_3 pr16b pl9a/pclkt7_0 pr15b pt17b/pclkc0_0 pr11a/d7/spid0 pr11b/busy/sispi pr12b/di/csspi* v3_3 6 10 8 4 1 2 35 7 9 conn_10p 2 37 13 8 59 11 6 4 10 12 14 1 conn_14p 2 37 13 8 59 11 6 4 10 12 14 1 conn_14p v3_3 v3_3 downloaded from: http:///
10k mem_cs mem_sck mem_si mem_so 2.7v 10k l_tdi l_tdo l_tms l_tck v1_2 l_tms v1_2 .1uf .1uf .1uf 10uf 10uf 10uf 97_io 10k mem_sck l_tdo l_tck l_tdi reset_sys rb33 rb20 u05 cb56 cb44 c20 cb67 cb45 c18 j12 ub06 ub09 rp06 17/19(total) 5/7(block) 02/06/2007 steve scully block name: _motprocrescard_dn. parent block: \_ztopdn_\ DS33Z11DK02a0 36 1 52 28 63 12 11 128 117 109 72 80 37 144 15 96 98 97 14 24 44 13 92 17 91 89 90 94 136 93 95 143 110 125 108 38 71 73 18 16 99 19 54 126 10 84 55 1 9 57 3 4 26 10 8 1 6 2 87 34 5 1 5 64 2 3 3 1 2 5 6 7 8 4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1963 shdn* gnd rst* out ic in v3_3 at25160a_u si gnd wp* hold* vcc so sck cs* conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo v3_3 v3_3 control lfec_t144_u all low for spi3 mode needs 10k,1% resistor place close to pin vccio4a vccio3b xres vccaux2 vccaux1 vccj vcc3 tdi tdo vccio3a vccio4b vccio5a vccio2 vccio1b vccio1a vccio0b init* program* vccio0a cclk cfg1 cfg2 cfg0 tms vcc2 vcc1 vccio5b vccio6a tck done gnd10 gnd9 gnd8 gnd7/gnd0 gnd6b/gnd5 gnd3b gnd3a/gnd4 gnd2/gnd1 gnd1 gnd0 nc1 nc2 gnd4 gnd6a gnd5 vccio7 vccio6b v3_3 downloaded from: http:///
trace geometry for this is: 1 inch long, 10 mil wide, 1 oz coppe r 5v dc power supply and reverse bias protection traces between regulator output and v3.3 should be long enough to build 0.06 ohm of resistance to ensure load sharing between the 3.3v 1% regulators 3.3v 1% regulator 3.3v 1% regulator reset_sys 330 supply_output regulator2_output regulator_input regulator_input regulator_input regulator_input regulator1_output 3.3v 3.3v 10uf 68uf 68uf 10uf 10uf 2.1mm/5.5mm 3.3v 68uf 0.0 10uf 0.0 10uf 10uf .50standoff__nut 3.08v 10uf green 0.0 0.0 68uf regulator_input supply_output regulator3_output 3.3v 10uf regulator4_output rb01 c07 rb02 cb02 ub01 db01 j01 gnd_tp04 gnd_tp03 cb73 c01 c02 h03 h02 ub11 sw01 cb01 h01 h05 h06 c04 rb03 c06 cb03 rb04 c05 ub04 ub02 ub03 rpb15 ds11 h04 c03 cb12 gnd_tp02 gnd_tpb01 block name: _motprocrescard_dn. parent block: \_ztopdn_\ 18/19(total) 6/7(block) 02/06/2007 steve scully DS33Z11DK02a0 2 1 2 1 1 1 1 1 1 1 1 1 1 3 1 42 43 1 2 2 1 2 1 1 1 1 2 1 15 67 13 5 4 2 17 10 11 14 12 3 15 67 13 5 4 2 17 10 11 14 12 3 15 67 13 5 4 2 17 10 11 14 12 3 3 1 2 5 6 7 8 4 1 2 2 1 15 67 13 5 4 2 17 10 11 14 12 3 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 v3_3 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 4 4 4 v3_3 max811_u reset* vcc gnd mr* 4 4 4 v5_0 v3_3 downloaded from: http:///
end of processor hierarchy block gnd v3_3 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .01uf .01uf .01uf .01uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf .1uf .1uf .1uf .01uf .01uf .01uf .01uf i67 i68 cb78 cb80 cb54 c36 cb93 cb96 cb37 cb19 cb35 cb90 cb82 cb86 cb88 c45 cb42 cb43 cb100 c25 c28 c21 c37 c22 c40 cb27 cb34 c38 c39 cb98 cb30 cb72 c34 c35 c26 cb59 cb69 cb65 cb57 cb48 cb62 cb25 c15 cb75 cb24 c42 cb94 cb91 cb84 cb87 cb74 cb50 cb83 cb61 c46 cb85 c43 c47 c41 cb99 cb97 cb47 cb55 c24 cb76 cb41 cb81 cb77 cb79 cb53 c32 c33 cb58 cb71 cb29 cb51 cb66 cb68 cb31 cb38 cb89 cb92 7/7(block) DS33Z11DK02a0 steve scully 02/06/2007 19/19(total) block name: _motprocrescard_dn. parent block: \_ztopdn_\ page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 v3_3 downloaded from: http:///

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